1. Field of the Invention
The present invention relates to packaging technology for semiconductor elements, and more particularly to a semiconductor device packaged by sealing a semiconductor element with resin, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, in order to reduce a delay of a signal due to parasitic capacity between wires in a semiconductor element and a leak current in the element, a low dielectric layer having a dielectric constant of 3 or less has been used as a multi-layer wiring interlayer insulator of the semiconductor element. To achieve a lower dielectric constant of 2 or less, fine air pores of about 0.1 to 100 nm are formed within the dielectric layer to obtain a porous material including a solid portion and air having a smaller dielectric constant. Such a low dielectric film has a low strength in terms of material and is very vulnerable because fine air is contained therein.
On the other hand, the semiconductor element is cut out mechanically from a wafer with a grinding stone, mounted on a glass epoxy substrate or a lead frame made of iron or copper alloy and sealed with epoxy or silicon base resin so as to produce a semiconductor package. Because, at this time, a peripheral portion of the semiconductor element is cut out with the grinding stone, the peripheral end of the element becomes so steep as to be substantially at right angle and a multi-layer insulating layer on the element is exposed outside. The steep side surface of the semiconductor element indicates cleavage in which the crystal orientations of pure silicon are aligned, so that adhesion strength to the sealing resin is low (for example, Jpn. Pat. Appln. KOKAI Publication No. 2003-197564).
When a semiconductor package is formed, stress is applied on the upper surface, side surface and lower surface of the semiconductor element because of differences in thermal expansion coefficient among the sealing resin, the substrate, and the semiconductor element. In the semiconductor package as a structure, higher stress is applied as it leaves toward the periphery from the center, and particularly, a high stress is applied on the peripheral portion of the semiconductor element such as the peripheral end and the side surface of the element. Due to the stress, there is such a problem that peeling occurs within the low dielectric film or on the multi-layer wiring layer interface within the multi-layer wiring film on the surface of the semiconductor element incorporating the low dielectric film. The semiconductor element surface has a higher thermal stress as it goes toward its peripheral end and if the multi-layer insulating film is peeled even slightly, peeling among the inter-layers advances from the portion.
The side surface of the semiconductor element and a portion near a cut section of the semiconductor element cannot obtain a high adhesion strength to the sealing resin as described above. Therefore, the sealing resin on the side surface of the semiconductor element having a high thermal stress is peeled easily, and stress of the surface including multi-layer wiring near the peripheral end of the semiconductor element increases extremely, so that the peeling of the vulnerable low dielectric layer is accelerated, which is another problem.
If a semiconductor package is constructed by sealing a semiconductor element comprising a vulnerable interlayer insulating film having a low dielectric constant according to the conventional method, peeling occurs in the interlayer insulating film having a low dielectric constant due to stress applied to the peripheral portion of the semiconductor element, the reliability of the element is decreased, which is still another problem.